TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
Table 8-67. TCP2 Registers (continued)
EDMA BUS HEX ADDRESS RANGE
CONFIGURATION BUS HEX
ADDRESS RANGE
ACRONYM
REGISTER NAME
5000 0048
5001 0000
5003 0000
5004 0000
5005 0000
5006 0000
5007 0000
5008 0000
5009 0000
500A 0000
500B 0000
N/A
-
N/A
TCPOUT2
X0
TCP2 Output Parameters Register 2
TCP2 Data/Sys and Parity Memory
TCP2 Extrinsic Mem 0
N/A
W0
N/A
W1
TCP2 Extrinsic Mem 1
N/A
I0
TCP2 Interleaver Memory
TCP2 Output/Decision Memory
TCP2 Scratch Pad Memory
TCP2 Beta State Memory
TCP2 CRC Memory
N/A
O0
N/A
S0
N/A
T0
N/A
C0
N/A
B0
TCP2 Beta Prolog Memory
TCP2 Alpha Prolog Memory
N/A
A0
02BA 0000
TCPPID
TCP2 Peripheral Identification
Register [Value: 0x0002 1101]
N/A
N/A
N/A
N/A
N/A
N/A
02BA 004C
02BA 0050
TCPEXE
TCPEND
TCPERR
TCPSTAT
TCPEMU
-
TCP2 Execute Register
TCP2 Endian Register
TCP2 Error Register
TCP2 Status Register
TCP2 Emulation Register
Reserved
02BA 0060
02BA 0068
02BA 0070
02BA 005C - 02BB FFFF
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