TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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8.17 Serial RapidIO (SRIO) Port
The SRIO Port on the TCI6487/8 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the RapidIO interconnect in a base band board design can create a
homogeneous interconnect environment, providing even more connectivity and control among the
components. RapidIO is based on the memory and device addressing concepts of processor buses where
the transaction processing is managed completely by hardware. This enables the RapidIO interconnect to
lower the system cost by providing lower latency, reduced overhead of packet data processing, and higher
system bandwidth, all of which are key for wireless interfaces. The RapidIO interconnect offers very low
pin-count interfaces with scalable system bandwidth based on 10-Gigabit per second (Gbps) bidirectional
links.
The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each
serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters.
The RapidIO interface should be designed to operate at a data rate up to 3.125 Gbps per differential pair.
8.17.1 SRIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as
McBSP. For these other interfaces the device timing was specified in terms of data manual specifications
and I/O buffer information specification (IBIS) models.
For the SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing two
DSPs connected via a 1x SRIO link directly to the user. TI has performed the simulation and system
characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system
solution is documented in the TMS320TCI6488 DSP SERDES Implementation Guidelines application
report (literature number SPRAAG7).
TI only supports designs that follow the board design guidelines outlined in the SPRAAG7
application report.
The Serial RapidIO peripheral is a master peripheral in the TCI6487/8 DSP. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2.
8.17.2 SRIO Register Description(s)
Table 8-68. RapidIO Control Registers
HEX ADDRESS
02D0 0000
ACRONYM
RIOPID
REGISTER NAME
RapidIO Peripheral Identification Register
RapidIO Peripheral Control Register
Reserved
02D0 0004
RIO_PCR
02D0 0008 - 02D0 001C
02D0 0020
-
RIO_PER_SET_CNTL
-
RapidIO Peripheral Settings Control Register
Reserved
02D0 0024 - 02D0 002C
02D0 0030
RIO_GBL_EN
RIO_GBL_EN_STAT
RIO_BLK0_EN
RIO_BLK0_EN_STAT
RIO_BLK1_EN
RIO_BLK1_EN_STAT
RIO_BLK2_EN
RIO_BLK2_EN_STAT
RIO_BLK3_EN
RIO_BLK3_EN_STAT
RIO_BLK4_EN
RapidIO Peripheral Global Enable Register
RapidIO Peripheral Global Enable Status Register
RapidIO Block0 Enable Register
RapidIO Block0 Enable Status Register
RapidIO Block1 Enable Register
RapidIO Block1 Enable Status Register
RapidIO Block2 Enable Register
RapidIO Block2 Enable Status Register
RapidIO Block3 Enable Register
RapidIO Block3 Enable Status Register
RapidIO Block4 Enable Register
02D0 0034
02D0 0038
02D0 003C
02D0 0040
02D0 0044
02D0 0048
02D0 004C
02D0 0050
02D0 0054
02D0 0058
164
Peripheral Information and Electrical Specifications
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