TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.8 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5-18 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-18).
Table 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
5416-120
5416-160
PARAMETER
UNIT
MIN
– 1
MAX
td(CLKL-IAQL)
td(CLKL-IAQH)
td(CLKL-IACKL)
td(CLKL-IACKH)
td(CLKL-A)
Delay time, CLKOUT low to IAQ low
4
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
Delay time, CLKOUT low to IAQ high
Delay time, CLKOUT low to IACK low
Delay time, CLKOUT low to IACK high
Delay time, CLKOUT low to address valid
Pulse duration, IAQ low
– 1
– 1
– 1
– 1
tw(IAQL)
2H – 2
2H – 2
tw(IACKL)
Pulse duration, IACK low
CLKOUT
t
d(CLKL−A)
t
d(CLKL−A)
A[22:0]
t
t
t
d(CLKL−IAQH)
d(CLKL−IAQL)
t
w(IAQL)
IAQ
t
d(CLKL−IACKH)
d(CLKL−IACKL)
t
w(IACKL)
IACK
Figure 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
76
Electrical Specifications
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