TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.10 Multichannel Buffered Serial Port (McBSP) Timing
5.5.10.1 McBSP Transmit and Receive Timings
Table 5-20 and Table 5-21 assume testing over recommended operating conditions (see Figure 5-21 and
Figure 5-22).
Table 5-20. McBSP Transmit and Receive Timing Requirements(1)
5416-120
5416-160
UNIT
MIN MAX
tc(BCKRX)
tw(BCKRX)
Cycle time, BCLKR/X(2)
Pulse duration, BCLKR/X high or BCLKR/X low(2)
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
4P(3)
2P–1(3)
ns
ns
8
1
1
2
7
1
2
3
8
1
0
2
tsu(BFRH-BCKRL)
th(BCKRL-BFRH)
tsu(BDRV-BCKRL)
th(BCKRL-BDRV)
tsu(BFXH-BCKXL)
th(BCKXL-BFXH)
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
ns
ns
ns
ns
ns
ns
Hold time, BDR valid after BCLKR low
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
tr(BCKRX)
tf(BCKRX)
Rise time, BCKR/X
Fall time, BCKR/X
6
6
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If the polaritiy of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be
achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A
separate detailed timing analysis should be performend for each specific McBSP interface.
(3) P = 0.5 * processor clock.
78
Electrical Specifications
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