TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
I/O(1)
DESCRIPTION
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
READY
R/W
I
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
IOSTRB
HOLD
O/Z
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the device, these lines go into the high-impedance state.
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low. Figure 2-2 This pin is driven high
during reset.
HOLDA
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
MSC
IAQ
O/Z
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when OFF is low.
TIMER SIGNALS
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the ma-
chine-cycle rate divided by 4.
CLKOUT
O/Z
I
Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock modes
such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled to determine
the desired clock generation mode while RS is low. Following reset, the clock generation mode can be
reconfigured by writing to the internal clock mode register in software.
CLKMD1(2)
CLKMD2(2)
CLKMD3(2)
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is
revision-dependent, see Section Section 3.10 for additional information.)
X2/CLKIN(2)
X1
I
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see
Section Section 3.10 for additional information.)
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
TOUT
O/Z
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),AND
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0(2)
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BCLKR1(2)
BCLKR2(2)
I/O/Z
I
BDR0, BDR1,
BDR2
Serial data receive input
BFSR0,
BFSR1,
BFSR2
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
I/O/Z
BCLKX0(2)
BCLKX1(2)
BCLKX2(2)
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state
when OFF goes low.
I/O/Z
O/Z
BDX0, BDX1,
BDX2
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0,
BFSX1,
BFSX2
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX
goes into the high-impedance state when OFF is low.
I/O/Z
14
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