TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HOLD and HOLDA timings
timing requirements for memory control signals and HOLDA, [H = 0.5 t
c(CO)
] (see Figure 21)
MIN
tw(HOLD)
tsu(HOLD)
Pulse duration, HOLD low
Setup time, HOLD low/high before CLKOUT low
4H+7
7
MAX
UNIT
ns
ns
switching characteristics over recommended operating conditions for memory control signals
and HOLDA, [H = 0.5 t
c(CO)
] (see Figure 21)
PARAMETER
tdis(CLKL-A)
tdis(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-A)
ten(CLKL-RW)
ten(CLKL-S)
tv(HOLDA)
tw(HOLDA)
CLKOUT
tsu(HOLD)
tw(HOLD)
HOLD
tv(HOLDA)
tv(HOLDA)
tw(HOLDA)
tdis(CLKL-A)
A[19:0]
PS, DS, IS
tsu(HOLD)
Disable time, address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, address, PS, DS, IS from CLKOUT low
Enable time, R/W enabled from CLKOUT low
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
Valid time, HOLDA low after CLKOUT low
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2
–1
–1
2H–1
MIN
MAX
5
5
5
2H+5
2H+5
2H+5
2
2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
HOLDA
ten(CLKL-A)
D[15:0]
tdis(CLKL-RW)
R/W
tdis(CLKL-S)
MSTRB
tdis(CLKL-S)
IOSTRB
ten(CLKL-S)
ten(CLKL-S)
ten(CLKL-RW)
Figure 21. HOLD and HOLDA Timings (HM = 1)
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
49
TI [ TEXAS INSTRUMENTS ]
