T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states
†
timing requirements for externally generated wait states [H = 0.5 t
Figure 19, and Figure 20)
] (see Figure 17, Figure 18,
c(CO)
MIN
6
MAX
UNIT
ns
t
t
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
su(RDY)
0
ns
h(RDY)
‡
Valid time, READY after MSTRB low
4H–8
5H–8
ns
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
v(MSCL)
‡
Hold time, READY after MSTRB low
4H
ns
‡
Valid time, READY after IOSTRB low
ns
‡
Hold time, READY after IOSTRB low
5H
–1
–1
ns
Valid time, MSC low after CLKOUT low
Valid time, MSC high after CLKOUT low
3
3
ns
ns
v(MSCH)
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
‡
CLKOUT
A[19:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(MSCH)
t
v(MSCL)
Wait State
Generated
by READY
Wait States
Generated Internally
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 17. Memory Read With Externally Generated Wait States
45
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