T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[19:0]
D[15:0]
t
h(RDY)
t
su(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(MSCH)
t
v(MSCL)
Wait States
Generated Internally
Wait State Generated
by READY
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 18. Memory Write With Externally Generated Wait States
46
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