T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t
†
] (see Figure 15)
c(CO)
MIN
MAX
3H–7
2H–7
UNIT
ns
t
t
t
t
t
Access time, read data access from address valid
Access time, read data access from IOSTRB low
Setup time, read data before CLKOUT high
Hold time, read data after CLKOUT high
a(A)IO
ns
a(ISTRBL)IO
su(D)IOR
6
0
0
ns
ns
h(D)IOR
Hold time, read data after IOSTRB high
ns
h(ISTRBH-D)R
†
Address and IS timings are included in timings referenced as address.
switching characteristics over recommended operating conditions for a parallel I/O port read
†
(IOSTRB = 0) (see Figure 15)
PARAMETER
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to IOSTRB high
Hold time, address after CLKOUT low
MIN
–2
–2
–2
0
MAX
UNIT
ns
t
3
3
3
3
d(CLKL-A)
t
ns
d(CLKH-ISTRBL)
t
ns
d(CLKH-ISTRBH)
t
ns
h(A)IOR
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
t
h(A)IOR
d(CLKL-A)
A[19:0]
t
h(D)IOR
t
su(D)IOR
t
a(A)IO
D[15:0]
t
h(ISTRBH-D)R
d(CLKH-ISTRBH)
t
a(ISTRBL)IO
t
t
d(CLKH-ISTRBL)
IOSTRB
R/W
IS
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 15. Parallel I/O Port Read (IOSTRB = 0)
43
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