T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing
timing requirements for a memory read (MSTRB = 0) [H = 0.5 t
†
] (see Figure 13)
c(CO)
MIN
MAX
2H–7
2H–8
UNIT
ns
t
t
t
t
t
Access time, read data access from address valid
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
Hold time, read data after CLKOUT low
a(A)M
ns
a(MSTRBL)
su(D)R
6
–2
0
ns
ns
h(D)R
Hold time, read data after address invalid
ns
h(A-D)R
t
Hold time, read data after MSTRB high
0
ns
h(D)MSTRBH
†
Address, PS, and DS timings are all included in timings referenced as address.
switching characteristics over recommended operating conditions for a memory read
†
(MSTRB = 0) (see Figure 13)
PARAMETER
MIN
–2
–2
–1
–1
–2
–2
MAX
UNIT
ns
‡
t
t
Delay time, CLKOUT low to address valid
3
3
3
3
3
3
d(CLKL-A)
§
Delay time, CLKOUT high (transition) to address valid
Delay time, CLKOUT low to MSTRB low
ns
d(CLKH-A)
t
ns
d(CLKL-MSL)
t
Delay time, CLKOUT low to MSTRB high
ns
d(CLKL-MSH)
‡
t
Hold time, address valid after CLKOUT low
ns
h(CLKL-A)R
h(CLKH-A)R
§
t
Hold time, address valid after CLKOUT high
ns
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read
In the case of a memory read preceded by a memory write
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