T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a memory write
†
(MSTRB = 0) [H = 0.5 t
] (see Figure 14)
c(CO)
PARAMETER
MIN
–2
MAX
UNIT
ns
‡
t
t
Delay time, CLKOUT high to address valid
3
d(CLKH-A)
§
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to data valid
Delay time, CLKOUT low to MSTRB high
Delay time, CLKOUT high to R/W low
Delay time, CLKOUT high to R/W high
Delay time, R/W low to MSTRB low
–2
3
ns
d(CLKL-A)
t
–1
3
ns
d(CLKL-MSL)
t
0
6
ns
d(CLKL-D)W
t
–1
3
ns
d(CLKL-MSH)
t
–1
3
3
ns
d(CLKH-RWL)
t
–1
ns
d(CLKH-RWH)
t
H – 2
1
H + 1
3
ns
d(RWL-MSTRBL)
‡
t
Hold time, address valid after CLKOUT high
ns
h(A)W
§
t
t
t
t
t
t
Hold time, write data valid after MSTRB high
Pulse duration, MSTRB low
H–3 H+6
ns
ns
ns
ns
ns
ns
h(D)MSH
w(SL)MS
su(A)W
2H–2
Setup time, address valid before MSTRB low
Setup time, write data valid before MSTRB high
Enable time, data bus driven after R/W low
Disable time, R/W high to data bus high impedance
2H–2
§
2H–6 2H+5
H–5
su(D)MSH
en(D–RWL)
dis(RWH–D)
0
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory write preceded by a memory write
In the case of a memory write preceded by an I/O cycle
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
