T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
†
(IOSTRB = 0) [H = 0.5 t
] (see Figure 16)
c(CO)
PARAMETER
MIN MAX
UNIT
ns
t
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to write data valid
Delay time, CLKOUT high to IOSTRB high
Delay time, CLKOUT low to R/W low
–2
–2
3
3
d(CLKL-A)
t
ns
d(CLKH-ISTRBL)
t
H–5
–2
H+8
3
ns
d(CLKH-D)IOW
t
ns
d(CLKH-ISTRBH)
t
–1
3
ns
d(CLKL-RWL)
d(CLKL-RWH)
t
t
t
t
t
Delay time, CLKOUT low to R/W high
–1
3
ns
Hold time, address valid after CLKOUT low
Hold time, write data after IOSTRB high
Setup time, write data before IOSTRB high
Setup time, address valid before IOSTRB low
0
H–3
H–7
H–2
3
H+7
H+1
H+2
ns
ns
ns
ns
h(A)IOW
h(D)IOW
su(D)IOSTRBH
su(A)IOSTRBL
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
su(A)IOSTRBL
t
h(A)IOW
t
d(CLKL-A)
A[19:0]
t
d(CLKH-D)IOW
t
h(D)IOW
D[15:0]
t
d(CLKH-ISTRBL)
t
d(CLKH-ISTRBH)
t
su(D)IOSTRBH
t
IOSTRB
R/W
t
d(CLKL-RWL)
d(CLKL-RWH)
IS
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 16. Parallel I/O Port Write (IOSTRB = 0)
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
