T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial ports
The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow
direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:
D
D
D
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
D
Direct interface to:
–
–
–
–
T1/E1 framers
MVIP switching compatible and ST-BUS compliant devices
IOM-2 compliant devices
Serial peripheral interface devices
D
D
D
D
D
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
D
D
D
D
D
D
BCLKX
BDX
BFSX
BCLKR
BDR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
BFSR
Receive frame synchronization
The six pins listed are functionally equivalent to previous serial port interface pins in the ’C5000 family of DSPs.
On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins,
respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR).
Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows
DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
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