T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
programmable bank-switching wait states
The programmable bank-switching logic of the ’5402 is functionally equivalent to that of the ’548/’549 devices.
This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or
data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the
data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 6
shows the BSCR and its bits are described in Table 4.
15
12
11
10
3
2
1
0
BNKCMP
R/W-1111
PS-DS
Reserved
R-0
HBH
BH
EXIO
R/W-1
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write
Figure 6. Bank-Switching Control Register (BSCR), MMR Address 0029h
Table 4. Bank-Switching Control Register (BSCR) Fields
BIT
NAME
RESET
VALUE
FUNCTION
NO.
Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
15–12 BNKCMP
1111
an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting in a
bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
Program read – data read access. Inserts an extra cycle between consecutive accesses of program read
and data read or data read and program read.
11
10–3
2
PS - DS
Reserved
HBH
1
0
0
PS-DS = 0
PS-DS = 1
No extra cycles are inserted by this feature.
One extra cycle is inserted between consecutive data and program reads.
These bits are reserved and are unaffected by writes.
HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.
HBH = 0
HBH = 1
The bus holder is disabled.
The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
BH = 1
The bus holder is disabled.
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
1
0
BH
0
0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
EXIO = 1
The external bus interface functions as usual.
The address bus, data bus, and control signals become inactive after completing the
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
EXIO
18
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