ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
functional block and CPU (DSP core) diagram
C6211/C6211B Digital Signal Processors
SDRAM
External
SBSRAM
32
Memory
Interface
(EMIF)
L1P Cache
Direct Mapped
4K Bytes Total
SRAM
ROM/FLASH
I/O Devices
Timer 0
Timer 1
C6000 CPU (DSP Core)
Instruction Fetch
Control
L2
Registers
Instruction Dispatch
Instruction Decode
Memory
4 Banks
64K Bytes
Total
Enhanced
DMA
Controller
(16 channel)
Control
Logic
Multichannel
Buffered
Serial Port 1
(McBSP1)
Data Path A
Data Path B
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Test
A Register File
B Register File
In-Circuit
Emulation
Multichannel
Buffered
Serial Port 0
(McBSP0)
Interrupt
Control
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
L1D Cache
2-Way Set
Associative
4K Bytes Total
Host Port
Interface
(HPI)
16
Power-Down
Logic
PLL
(x1, x4)
Boot
Configuration
Interrupt
Selector
8
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