ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
CPU (DSP core) description (continued)
src1
src2
.L1
dst
long dst
long src
8
8
32
ST1
8
long src
long dst
dst
Register
File A
Data Path A
.S1
src1
(A0−A15)
src2
dst
src1
.M1
src2
LD1
dst
src1
src2
.D1
.D2
DA1
2X
1X
src2
src1
dst
DA2
LD2
src2
.M2
.S2
src1
dst
src2
Register
File B
(B0−B15)
Data Path B
src1
dst
long dst
long src
8
32
8
ST2
8
long src
long dst
dst
.L2
src2
src1
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths
10
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