TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
direct memory access unit (DMA) (continued)
Hex
Data
Hex
Program Page 0
Hex
Program Page 1
Hex
Program Page 2
Reserved
Hex
Program Page 3
Reserved
Hex
I/O
0000
0000
10000
20000
30000
DMA FIFO
for Core-Core
Communication
Reserved
Reserved
001F
0020
001F
0020
XXXX
{
Reserved
McBSP
DXR/DRR
MMRegs Only
McBSP
DXR/DRR
MMRegs Only
005F
0060
005F
0060
1005F
10060
2005F
20060
3005F
30060
Scratch-Pad
DARAM
007F
0080
On-Chip
DARAM 0
On-Chip
DARAM 0
(Overlayed)
Prog/Data
On-Chip
DARAM 0
(Overlayed)
Prog/Data
On-Chip
DARAM 0
(Overlayed)
Prog/Data
On-Chip
DARAM 0
(16K Words)
(Overlayed)
Prog/Data
23FFF
24000
3FFF
4000
3FFF
4000
13FFF
14000
33FFF
34000
On-Chip
SARAM 1
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(Overlayed)
Prog/Data
On-Chip
SARAM 1
(16K Words)
7FFF
8000
7FFF
8000
17FFF
18000
27FFF
28000
37FFF
38000
Reserved
2EFFF
2F000
On-Chip
SARAM 2
On-Chip
SARAM 2
On-Chip
SARAM 3
Reserved
(32K Words)
Prog/Data
(32K Words)
Prog/Data
(32K Words)
Prog/Data
On-Chip
SARAM 4
(4K Words)
Prog/Data
FFFF
FFFF
1FFFF
2FFFF
3FFFF
†
When the source or destination for a DMA channel is programmed for I/O space, the channel accesses the core-to-core FIFO irrespective of
the address specified.
Figure 7. Memory Map Relative to DMA
features
The ’5420 DMA has the following features:
D
D
D
D
D
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address can remain constant, postincrement,
postdecrement or be adjusted by a programmable value.
D
D
D
D
Each read or write transfer can be initialized by selected events.
On completion of a half-block or full-block transfer, each DMA channel can send an interrupt to the CPU.
An on-chip RAM DMA transfer requires 4 clock cycles to complete. External transfers are not supported.
The DMA can perform double word transfers (a 32-bit transfer of two16-bit-words).
27
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