TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
downloading code during reset
The HPI16 can download code while the DSP is in reset. However, the system provides a pin (HPIRS) that
provides a way to take the HPI16 module out of reset while leaving the DSP in reset.
emulation considerations
The HPI16 can continue operation even when the DSP CPU is halted due to debugger breakpoints or other
emulation events.
5420 boundary scan implementation
The ’5420 does not implement a fully compliant IEEE1149.1 boundary scan capability. Observe-only boundary
scan cells are used on all of the device pins that allow the pins to be observed (read) but not controlled (driven)
using boundary scan. Driving nodes to perform board interconnect test must be accomplished using other
boundary scan capable devices on the board. Although this implies some reduction in testability, compared to
full boundary scan, this implementation is still compatible with the boundary scan automatic test pattern
generation (ATPG) tools.
multichannel buffered serial port (McBSP)
The ’5420 device provides high-speed, full-duplex serial ports that allow direct interface to other ’C54x devices,
codecs, and other devices in a system. There are six multichannel buffered serial ports (McBSPs) on chip (three
per subsystem).
The McBSP is based on the standard serial port interface found on the ’54x devices. Like its predecessors, the
McBSP provides:
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Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
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Direct interface to:
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T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant device
Serial peripheral interface devices
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Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and
BCLKR, connect the control and data paths to external devices. The pins can be programmed as
general-purpose I/O pins if they are not used for serial communication.
Like the standard serial port interface on the McBSP, the data is communicated to devices interfacing to the
McBSP by way of the data transmit (BDX) pin for transmit and the data receive (BDR) pin for receive. Control
information in the form of clocking and frame synchronization is communicated by way of BCLKX, BCLKR,
BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers accessible
via the internal peripheral bus. The CPU or DMA reads the received data from the data receive register (DRR)
and writes the data to be transmitted to the data transmit register (DXR). Data written to the DXR is shifted out
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