TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
FIFO data communications (continued)
other to flag when the FIFOs are either full or empty. The interprocessor interrupt request bit (IPIRQ) (bit 8 in
the BSCR register ) is set to “1” to generate an interprocessor interrupt (IPINT) in the other subsystem. See the
interrupts section for more information.
EMIF-to-HPI data communication
The ’5420 also provides the capability for one subsystem to act as a master and transfer data to the other
subsystem via an EMIF-to-HPI connection. The master device is configured in EMIF mode (XIO pin is high);
while by default, when HMODE=1, the slave device external interface is configured to operate as an HPI
(nonmultiplexed mode). The data-transfer direction is defined by the logic level of SELA/B. See Table 7 for a
complete description of HMODE, SELA/B, and XIO pin functionality. The EMIF-to-HPI option is bidirectional,
but does not permit full duplex communication without external SELA/B arbitration. This mode does not offer
master/slave interrupts due to the nonmultiplexed HPI configuration.
Table 7. EMIF/HPI Modes
HMODE
SELA/B
HPI MODES (XIO PIN =0)
EMIF MODES (XIO PIN = 1)
HPI multiplexed address/data
Subsystem A slave to host
Subsystem A can access EMIF
Subsystem B has no access to EMIF or HPI
0
0
HPI multiplexed address/data
Subsystem B slave to host
Subsystem B can access EMIF
Subsystem A has no access to EMIF or HPI
0
1
1
1
0
1
HPI nonmultiplexed address/data
Subsystem A slave to host
EMIF-to-HPI master is subsystem A, slave is
subsystem B
HPI nonmultiplexed address/data
Subsystem B slave to host
EMIF-to-HPI master is subsystem B, slave is
subsystem A
general-purpose I/O
In addition to the standard XF and BIO pins, the ’5420 has eight general-purpose I/O pins. These pins are:
A_GPIO0, A_GPIO1, A_GPIO2, A_GPIO3
B_GPIO0, B_GPIO1, B_GPIO2, B_GPIO3
Each subsystem’s CPU has one general-purpose I/O register located at address 0x3c in data memory. Each
I/O register controls four general-purpose I/O pins. Figure 8 shows the bit layout of the general-purpose I/O
control register and Table 8 describes the bit functions.
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