Electrical Specifications
5.15 Host-Port Interface Timing
5.15.1 HPI8 Mode
Table 5−33 and Table 5−34 assume testing over recommended operating conditions and P = 0.5 * processor
clock (see Figure 5−28 through Figure 5−31). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0,
HCNTL1, and HR/W.
Table 5−33. HPI8 Mode Timing Requirements
MIN
6
MAX
UNIT
ns
Setup time, HBIL valid before DS low (when HAS is not used), or HBIL valid before HAS
low
t
t
su(HBV-DSL)
Hold time, HBIL valid after DS low (when HAS is not used), or HBIL valid after HAS low
3
ns
h(DSL-HBV)
t
t
t
t
t
t
t
Setup time, HAS low before DS low
8
13
7
ns
ns
ns
ns
ns
ns
ns
su(HSL-DSL)
Pulse duration, DS low
w(DSL)
Pulse duration, DS high
w(DSH)
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
3
su(HDV-DSH)
h(DSH-HDV)W
2
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
3
su(GPIO-COH)
h(GPIO-COH)
0
100
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
