Functional Overview
3.12.1 Features
The DMA has the following features:
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The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for both internal and external accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
be post-decremented, or be adjusted by a programmable value.
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Each read or write internal transfer may be initialized by selected events.
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
3.12.2 DMA External Access
The 5407/5404 DMA supports external accesses to extended program, extended data, and extended I/O
memory. These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can
be used for external memory accesses. The DMA external accesses require a minimum of 8 cycles for external
writes and a minimum of 11 cycles for external reads assuming the XIO02 is in consecutive mode
(CONSEC = 1), wait state is set to two, and CLKOUT is not divided (DIVFCT = 00).
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the
external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes
precedence over XIO requests.
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Only two channels are available for external accesses. (One for external reads and one for external
writes.)
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Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from the peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external-to-external transfers.
The DMA does not support synchronized external transfers.
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14
13
12
11
10
2
8
AUTOINIT
DINM
IMOD
CTMOD
SLAXS
SIND
1
7
6
5
4
0
DMS
DLAXS
DIND
DMD
Figure 3−18. DMA Transfer Mode Control Register (DMMCRn)
These new bit fields were created to allow the user to define the space-select for the DMA (internal/external).
Also, a new extended destination data page (XDSTDP[6:0], subaddress 029h) and extended source data
page (XSRCDP[6:0], subaddress 028h) have been created. The functions of the DLAXS and SLAXS bits are
as follows:
DLAXS(DMMCRn[5]) Destination
SLAXS(DMMCRn[11]) Source
0 = No external access (default internal)
1 = External access
0 = No external access (default internal)
1 = External access
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November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
