Peripherals
Figure 4−5 shows the ADC pin-biasing for internal reference and Figure 4−6 shows the ADC pin-biasing for
external reference.
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Test Pin
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
†
ADCBGREFIN
24.9 kꢀ/20 kꢀ (See Note C)
ADC External Current Bias Resistor ADCRESEXT
‡
‡
10 ꢁF
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
10 ꢁF
V
V
V
V
Analog 3.3 V
Analog 3.3 V
DDA1
DDA2
SSA1
SSA2
ADC Analog Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Reference Power
ADC Analog I/O Power
ADC Digital Power
V
V
Analog 3.3 V
Analog Ground
DDAIO
SSAIO
V
V
1.8 V
Digital Ground
can use the same 1.8 V (or 1.9 V) supply as
the digital core but separate the two with a
ferrite bead or a filter
DD1
SS1
†
‡
Provide access to this pin in PCB layouts. Intended for test purposes only.
TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. Use 24.9 kΩ for ADC clock range 1 − 18.75 MHz; use 20 kΩ for ADC clock range 18.75 − 25 MHz.
Figure 4−5. ADC Pin Connections With Internal Reference (See Notes A and B)
NOTE:
The temperature rating of any recommended component must match the rating of the end
product.
66
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
