Features
1
Features
D
High-Performance Static CMOS Technology
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
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128-Bit Security Key/Lock
− Protects Flash/ROM/OTP and L0/L1
SARAM
− Prevents Firmware Reverse Engineering
†
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D
JTAG Boundary Scan Support
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Motor Control Peripherals
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
High-Performance 32-Bit CPU
(TMS320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program/Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− TMS320F24x/LF240x Processor Source
Code Compatible
− Enhanced Controller Area Network
(eCAN)
− Multichannel Buffered Serial Port
(McBSP)
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12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
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On-Chip Memory
− Flash Devices: Up to 128K x 16 Flash
(Four 8K x 16 and Six 16K x 16 Sectors)
− ROM Devices: Up to 128K x 16 ROM
− 1K x 16 OTP ROM
− L0 and L1: 2 Blocks of 4K x 16 Each
Single-Access RAM (SARAM)
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
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Up to 56 General Purpose I/O (GPIO) Pins
Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
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Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Code Composer Studio IDE
− DSP/BIOS
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D
Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
†
− JTAG Scan Controllers
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D
Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
External Interface (2812)
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
Package Options
− 179-Ball MicroStar BGA With External
Memory Interface (GHH), (ZHH) (2812)
− 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)
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Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
− Watchdog Timer Module
− 128-Pin LQFP Without External Memory
Interface (PBK) (2810, 2811)
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D
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Three External Interrupts
Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
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Temperature Options:
− A: −40°C to 85°C (GHH, ZHH, PGF, PBK)
− S/Q: −40°C to 125°C (GHH, ZHH, PGF,
PBK)
Three 32-Bit CPU-Timers
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
13
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
