ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉꢄ ꢅ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢇꢍꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
†
(IOSTRB = 0) [H = 0.5 t
] (see Figure 18)
c(CO)
PARAMETER
MIN
−1
0
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
t
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to write data valid
Delay time,CLKOUT high to IOSTRB high
Delay time, CLKOUT low to R/W low
5
5
d(CLKL-A)
ns
d(CLKH-ISTRBL)
d(CLKH-D)IOW
d(CLKH-ISTRBH)
d(CLKL-RWL)
d(CLKL-RWH)
h(A)IOW
H−5 H+11
ns
0
0
5
4
ns
ns
Delay time, CLKOUT low to R/W high
0
4
ns
Hold time, address valid after CLKOUT low
Hold time, write data after IOSTRB high
Setup time, write data before IOSTRB high
Setup time, address valid before IOSTRB low
−1
H−3
5
ns
H+5
ns
h(D)IOW
3H−9 3H+5
ns
su(D)IOSTRBH
su(A)IOSTRBL
H−3
H+3
ns
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
su(A)IOSTRBL
t
h(A)IOW
t
d(CLKL-A)
PPA[17:0]
t
d(CLKH-D)IOW
t
h(D)IOW
PPD[15:0]
t
d(CLKH-ISTRBL)
t
d(CLKH-ISTRBH)
t
su(D)IOSTRBH
IOSTRB
R/W
t
t
d(CLKL-RWH)
d(CLKL-RWL)
IS
1 Wait State
Figure 18. Parallel I/O Port Write (IOSTRB=0)
52
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