ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
ready timing for externally generated wait states
†
timing requirements for externally generated wait states [H = 0.5 t
Figure 16)
] (see Figure 15 and
c(CO)
MIN
7
MAX
UNIT
ns
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
su(RDY)
0
ns
h(RDY)
‡
t
Valid time, READY after MSTRB low
4H−8
ns
v(RDY)MSTRB
‡
t
Hold time, READY after MSTRB low
4H
ns
h(RDY)MSTRB
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT
‡
CLKOUT
A[19:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
t
v(RDY)MSTRB
t
h(RDY)MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
Figure 15. Memory Read With Externally Generated Wait States
49
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