ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉꢄ ꢅ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢇꢍꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
external memory interface timing for a memory write for one wait state (continued)
CLKOUT
t
d(CLKH-A)
t
d(CLKL-A)
t
h(A)W
A[19:0]
D[15:0]
MSTRB
R/W
t
d(CLKL-D)W
t
h(D)MSH
t
su(D)MSH
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
su(A)W
t
d(CLKH-RWL)
t
d(CLKH-RWH)
t
w(SL)MS
t
d(RWL-MSTRBL)
PS, DS
1 Wait State
Figure 14. Memory Write (MSTRB = 0)
48
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