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ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
reset, BIO, interrupt, and XIO timing
timing requirements for reset, BIO, interrupt, and XIO [H = 0.5 t
and Figure 23)
] (see Figure 21, Figure 22,
c(CO)
MIN
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
Hold time, A_RS or B_RS after CLKOUT low
Hold time, BIO after CLKOUT low
h(RS)
h(BIO)
h(INT)
h(XIO)
0
†
Hold time, INTn, NMI, after CLKOUT low
0
‡
Hold time, XIO after CLKOUT low
0
§¶
Pulse duration, A_RS or B_RS low
4H+5
5H
4H
4H
8
w(RSL)
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (asynchronous)
w(BIO)A
w(INTH)A
w(INTL)A
†
†
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
†
t
w(INTL)WKP
¶
t
Setup time, A_RS or B_RS before CLKIN low
Setup time, BIO before CLKOUT low
7
su(RS)
su(BIO)
su(INT)
su(XIO)
t
t
t
9
†
Setup time, INTn, NMI, A_RS or B_RS before CLKOUT low
Setup time, XIO before CLKOUT low
9
‡
10
†
The external interrupts (INT0−INT1, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to a three-CLKOUT sampling sequence.
Once the setup and hold times are met for XIO, the following falling edge of CLKOUT is either an HPI or EMIF cycle.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, A_RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
‡
§
¶
Note that A_RS can cause a change in clock frequency, therefore changing the value of H (see the software-programmable phase-locked loop
(PLL) section).
CLKIN
t
su(RS)
t
w(RSL)
A_RS, B_RS,
INTn, NMI
t
su(INT)
t
h(RS)
CLKOUT
t
su(BIO)
t
h(BIO)
BIO
t
w(BIO)S
Figure 21. Reset and BIO Timings
55
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