ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
external memory interface timing for a memory write for one wait state
switching characteristics over recommended operating conditions for a memory write
†
(MSTRB = 0) [H = 0.5 t
] (see Figure 14)
c(CO)
PARAMETER
MIN
− 1
−1
MAX
UNIT
ns
‡
t
t
t
t
t
t
t
Delay time, CLKOUT high to address valid
6
d(CLKH-A)
§
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to data valid
Delay time, CLKOUT low to MSTRB high
Delay time, CLKOUT high to R/W low
Delay time, CLKOUT high to R/W high
Delay time, R/W low to MSTRB low
5
ns
d(CLKL-A)
−1
4
ns
d(CLKL-MSL)
d(CLKL-D)W
d(CLKL-MSH)
d(CLKH-RWL)
d(CLKH-RWH)
0
12
ns
− 1
0
4
ns
4
4
ns
−1
ns
t
H − 2
−1
H + 2
6
ns
d(RWL-MSTRBL)
‡
t
Hold time, address valid after CLKOUT high
ns
h(A)W
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory write preceded by a memory write
In the case of a memory write preceded by an I/O cycle.
†
timing requirements for a memory write (MSTRB = 0) [H = 0.5 t
] (see Figure 14)
c(CO)
MIN
H − 3
4H−4
H−4
MAX
UNIT
ns
§
H +3
t
t
t
t
Hold time, write data valid after MSTRB high
h(D)MSH
w(SL)MS
su(A)W
§
Pulse duration, MSTRB low
ns
Setup time, address valid before MSTRB low
Setup time, write data valid before MSTRB high
ns
§
4H−10
4H+5
ns
su(D)MSH
†
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory write preceded by an I/O cycle.
47
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