ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
memory
The total memory address range for each 5420 subsystem is 384K 16-bit words. The memory space is divided
into three specific memory segments: 256K-word program, 64K-word data, and 64K-word I/O. The program
memory space contains the instructions to be executed as well as tables used in execution. The data memory
space stores data used by the instructions. The I/O memory space is used to interface to external
memory-mapped peripherals and can also serve as extra data storage space. The CPU I/O space should not
be confused with the DMA I/O space, which is completely independent and not accessible by the CPU.
on-chip dual-access RAM (DARAM)
The 5420 subsystems A and B each have 16K × 16-bit on-chip DARAM (2 blocks of 8K words).
Each of these RAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store
data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory
space. DARAM can be mapped into program/data memory space by setting the OVLY bit in the PMST register.
on-chip single-access RAM (SARAM)
The 5420 subsystems A and B each have 80K-word × 16-bit on-chip SARAM (ten blocks of 8K words each).
Each of these SARAM blocks is a single-access memory. This memory is intended primarily to store data values;
however, it can be used to store program as well. At reset, the SARAM (4000h−7FFFh) is mapped into data
memory space. This memory range can be mapped into program/data memory space by setting the OVLY bit
in the PMST register. The SARAM at 8000h−FFFFh is program memory at reset and can be configured as
program/data memory by setting the DROM bit. SARAM space18000h−1FFFFh is mapped as program
memory only.
program memory
The 5420 device features a paged extended memory scheme in program space to allow access of up to 256K
of program memory relative to each subsystem. This extended program memory (each subsystem) is organized
into four pages (0−3), each 64K in length. A hardware pin is used to select which DSP subsystem (A or B) has
control of the external memory interface. To implement the extended program memory scheme, the 5420 device
includes the following features:
D
D
Two additional address lines (for a total of 18)
A pin (SELA/B) for external memory interface arbitration between subsystem A and B
data memory
The data memory space on each 5420 subsystem contains up to 64K 16-bit word addresses. The device
automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated
outside the RAM bounds, the device automatically generates an external access.
parallel I/O ports
Each subsystem of the 5420 has a total of 64K I/O ports. These ports can be addressed by PORTR and PORTW.
The IS signal indicates the read/write access through an I/O port. The devices can interface easily with external
devices through the I/O ports while requiring minimal off-chip address-decoding logic. The SELA/B pin selects
which subsystem has access to the external I/O space.
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