ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉꢄ ꢅ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢇꢍꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
HOST-PORT INTERFACE SIGNALS
HPI address inputs. HA[0:17] are used by the host device, in the HPI non-multiplexed
mode (HMODE pin is high), to address the on-chip RAM of the 5420. These pins are
shared with the external memory interface and are only used by the HPI when the interface
PRIMARY
HA[0:17]
I
PPA[0:17]
O
is in HPI mode (XIO pin is low).
Parallel bidirectional data bus. HD[0:15] are used by the host device to transfer data to
and from the on-chip RAM of the 5420. These pins are shared with the external memory
interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low).
The data bus includes bus holders to reduce power dissipation caused by floating, unused
I/O/Z
HD[0:15]
I/O/Z
PPD[0:15]
pins. The bus holders also eliminate the need for external pullup resistors on unused pins.
When the data bus is not being driven by the 5420, the bus holders keep data pins at the
last driven logic level. The data bus keepers are disabled at reset and can be
enabled/disabled via the BH bit of the BSCR register. These pins are placed into the
high-impedance state when OFF is low.
PRIMARY
HPI control inputs. The HCNTL0 and HCNTL1 values between HPIA, and HPID registers
during HPI reads and writes. These signals are only used in HPI multiplexed address/data
mode (HMODE pin is low).
These pins are shared with the external memory interface and are only used by the HPI
when the interface is in HPI mode (XIO pin is low).
HCNTL0
HCNTL1
PPA3
PPA2
I
I
O
O
Address strobe input. Hosts with multiplexed address and data pins require HAS to latch
the address in the HPIA register. This signal is only used in HPI multiplexed address/data
mode (HMODE pin is low).
‡§
HAS
‡§
PPA4
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
HPI chip-select signal. This signal must be active during HPI transfers, and can remain
active between concurrent transfers.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
‡§
‡§
MSTRB
HCS
I
I
I
O
O
O
HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes to control
transfer HPI transfers.
These pins are shared with the external memory interface and are only used by the HPI
when the interface is in HPI mode (XIO pin is low).
‡§
HDS1
‡§
HDS2
‡§
PS
‡§
DS
HPI read/write signal. This signal is used by the host to control the direction of an HPI
transfer.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
HR/W
R/W
HPI data-ready output. The ready output informs the host when the HPI is ready for the
next transfer.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low). HRDY is placed into the high-impedance state
when OFF is low.
HRDY
O
O
READY
I
Host interrupt pin. HPI can interrupt the host by asserting this low. The host can clear this
interrupt by writing a “1” to the HINT bit of the HPIC register. Only supported in HPI
multiplexed address/data mode (HMODE pin is low). These pins are placed into the
high-impedance state when OFF is low.
A_HINT
B_HINT
PPA0
PPA1
O
†
‡
§
¶
#
||
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
This pin is used by Texas Instruments for device testing and should be left unconnected.
This pin has an internal pulldown resistor.
kAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the V and V specifications are met.
IL
IH
14
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