Electrical Specifications
Table 5–22. McBSP
Transmit and Receive
Switching Characteristics
†
PARAMETER
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
td(BCKRH-BFRV)
td(BCKXH-BFXV)
Cycle time, BCLKR/X
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
Delay time BCLKR high to internal BFSR valid
time,
Delay time BCLKX high to internal BFSX valid
time,
BCLKR/X int
BCLKR/X int
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
BFSX ext
– 1¶
2
–1¶
2
MIN
4P‡
D – 1§
C – 1§
–3
0
–1
2
D + 1§
C + 1§
3
12
5
10
6
10
10
20
7
11
ns
ns
ns
ns
MAX
UNIT
ns
ns
ns
ns
ns
Disable time, BCLKX high to BDX high im edance following last data
impedance
tdis(BCKXH-BDXHZ)
bit of transfer
td(BCKXH-BDXV)
td(BFXH-BDXV)
Delay time BCLKX high to BDX valid
time,
DXENA = 0#
Delay time, BFSX high to BDX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 0.5 * processor clock
§ T = BCLKRX period = (1 + CLKGDV) * 2P
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶ Minimum delay times also represent minimum output hold times.
# The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5407/TMS320VC5404.
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
BCLKR
td(BCKRH-BFRV)
td(BCKRH-BFRV)
BFSR (int)
tsu(BFRH-BCKRL)
th(BCKRL-BFRH)
BFSR (ext)
tsu(BDRV-BCKRL)
BDR
Bit(n-1)
tr(BCKRX)
tf(BCKRX)
th(BCKRL-BDRV)
(n-2)
(n-3)
Figure 5–21. McBSP Receive Timings
November 2001 – Revised July 2003
SPRS007B
81
TI [ TEXAS INSTRUMENTS ]
