TMS320VC5407PGER 参数 Datasheet PDF下载

Functional Overview

Table 3–24. Peripheral Memory-Mapped Registers for Each DSP Subsystem

NAME

DRR20

DRR10

DXR20

DXR10

TIM

PRD

TCR

—

SWWSR

BSCR

—

SWCR

HPIC

—

DRR22

DRR12

DXR22

DXR12

SPSA2

SPSD2

—

SPSA0

SPSD0

—

GPIOCR

GPIOSR

CSIDR

—

DRR21

DRR11

DXR21

DXR11

USAR

USDR

—

SPSA1

SPSD1

—

TIM1

PRD1

TCR1

—

DMPREC

DMSA

DMSDI

DMSDN

CLKMD

—

ADDRESS

DEC

HEX

32

20

33

21

34

22

35

23

36

24

37

25

38

26

39

27

40

28

41

29

42

2A

43

2B

44

2C

45–47

2D–2F

48

30

49

31

50

32

51

33

52

34

53

35

54–55

36–37

56

38

57

39

58–59

3A–3B

60

3C

61

3D

62

3E

63

3F

64

40

65

41

66

42

67

43

68

44

69

45

70–71

46–47

72

48

73

49

74–75

4A–4B

76

4C

77

4D

78

4E

79–83

4F–53

84

54

85

55

86

56

87

57

88

58

89–95

59–5F

DESCRIPTION

McBSP 0 Data Receive Register 2

McBSP 0 Data Receive Register 1

McBSP 0 Data Transmit Register 2

McBSP 0 Data Transmit Register 1

Timer 0 Register

Timer 0 Period Register

Timer 0 Control Register

Reserved

Software Wait-State Register

Bank-Switching Control Register

Reserved

Software Wait-State Control Register

HPI Control Register (HMODE = 0 only)

Reserved

McBSP 2 Data Receive Register 2

McBSP 2 Data Receive Register 1

McBSP 2 Data Transmit Register 2

McBSP 2 Data Transmit Register 1

McBSP 2 Subbank Address Register†

McBSP 2 Subbank Data Register†

Reserved

McBSP 0 Subbank Address Register†

McBSP 0 Subbank Data Register†

Reserved

General-Purpose I/O Control Register

General-Purpose I/O Status Register

Device ID Register

Reserved

McBSP 1 Data Receive Register 2

McBSP 1 Data Receive Register 1

McBSP 1 Data Transmit Register 2

McBSP 1 Data Transmit Register 1

UART Subbank Address Register

UART Subbank Data Register

Reserved

McBSP 1 Subbank Address Register†

McBSP 1 Subbank Data Register†

Reserved

Timer 1 Register

Timer 1 Period Register

Timer 1 Control Register

Reserved

DMA Priority and Enable Control Register

DMA Subbank Address Register‡

DMA Subbank Data Register with Autoincrement‡

DMA Subbank Data Register‡

Clock Mode Register (CLKMD)

Reserved

† See Table 3–25 for a detailed description of the McBSP control registers and their subaddresses.

‡ See Table 3–26 for a detailed description of the DMA subbank addressed registers.

50

SPRS007B

November 2001 – Revised July 2003