Functional Overview
3.13.1
UART Accessible Registers
The system programmer has access to and control over any of the UART registers that are summarized in
Table 3–14. These registers control UART operations, receive data, and transmit data. Descriptions of these
registers follow Table 3–15. See Table 3–24 for more information on peripheral memory mapped registers.
Table 3–15. Summary of Accessible Registers
UART SUBBANK ADDRESS
0
(DLAB = 0)
BIT
NO.
Receiver
Buffer
Register
(Read
Only)
RBR
0
(DLAB = 0)
Transmitter
Holding
Register
(Write
Only)
THR
0 (DLAB = 1)
or 8
Divisor
Latch
(LSB)
DLL
1
(DLAB = 0)
Interrupt
Enable
Register
IER
Enable
Received
Data
Available
Interrupt
(ERBI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Enable
Receiver
Line Status
Interrupt
(ELSI)
0
‡
1 (DLAB = 1)
or 9
Divisor
Latch
(MSB)
DLM
2
Interrupt
Ident.
Register
(Read
Only)
IIR
2
FIFO
Control
Register
(Write
Only)
FCR
3
4
5
6
7
Line
Control
Register
LCR
Word
Length
Select
Bit 0
(WLS0)
Modem
Control
Register
MCR
Line
Status
Register
LSR
Re-
served
Register
RSV
Scratch
Register
SCR
0
Data Bit 0†
Data Bit 0
Bit 0
Bit 8
0 if
Interrupt
Pending
FIFO
Enable
X
Data
Ready
(DR)
X
Bit 0
1
Data Bit 1
Data Bit 1
Bit 1
Bit 9
Interrupt
ID
Bit 1
Receiver
FIFO
Reset
Word
Length
Select
Bit 1
(WLS1)
X
Overrun
Error
(OE)
X
Bit 1
2
Data Bit 2
Data Bit 2
Bit 2
Bit 10
Interrupt
ID
Bit 2
Interrupt
ID
Bit 3
§
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
Parity
Enable
(PEN)
Even
Parity
Select
(EPS)
Stick
Parity
X
Parity
Error
(PE)
Framing
Error
(FE)
Break
Interrupt
(BI)
Transmitter
Holding
Register
(THRE)
Transmitter
Empty
(TEMT)
Error in
RCVR
FIFO
§
0
X
Bit 2
3
Data Bit 3
Data Bit 3
Bit 3
Bit 11
0
‡
X
X
Bit 3
4
Data Bit 4
Data Bit 4
Bit 4
0
Bit 12
0
Reserved
Loop
X
Bit 4
5
Data Bit 5
Data Bit 5
Bit 5
0
Bit 13
0
Reserved
0
‡
X
Bit 5
6
Data Bit 6
Data Bit 6
Bit 6
0
Bit 14
FIFOs
Enabled
§
Receiver
Trigger
(LSB)
Receiver
Trigger
(MSB)
0
Break
Control
Divisor
Latch
Access
Bit
(DLAB)
0
0
X
Bit 6
7
Data Bit 7
Data Bit 7
Bit 7
0
Bit 15
FIFOs
Enabled
§
0
X
Bit 7
8 – 15
0
0
0
0
0
0
0
0
0
† Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
‡ Must always be written as zero.
§ These bits are always 0 in the TL16C450 mode.
NOTE: X = Don’t care for write, indeterminate on read.
40
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
