Functional Overview
3.12.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available
modes are shown in Table 3–11.
Table 3–11. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi frame
Multi frame
Either
Either
DINM
1
1
1
1
0
0
IMOD
0
1
0
1
X
X
At full buffer only
At half buffer and full buffer
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
No interrupt generated
INTERRUPT
3.12.11 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events
and the DSYN values are shown in Table 3–12.
Table 3–12. DMA Synchronization Events
DSYN VALUE
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
DMA SYNCHRONIZATION EVENT
No synchronization used
McBSP0 receive event
McBSP0 transmit event
McBSP2 receive event
McBSP2 transmit event
McBSP1 receive event
McBSP1 transmit event
UART
Reserved
Reserved
Reserved
Reserved
Reserved
Timer 0 interrupt event
External interrupt 3
Timer 1 interrupt event
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the 5407/5404 is reset, the interrupts from these three DMA channels are deselected. The INT0SEL bit field
in the DMPREC register can be used to select these interrupts, as shown in Table 3–13.
Table 3–13. DMA/CPU Channel Interrupt Selection
INT0SEL VALUE
00b (reset)
01b
10b
11b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
BXINT2
DMAC1
Reserved
IMR/IFR[10]
BRINT1
DMAC2
DMAC2
IMR/IFR[11]
BXINT1
DMAC3
DMAC3
36
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
