Functional Overview
Table 3–14. UART Reset Functions
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
FIFO control register
Line control register
Modem control register
Line status register
Reserved register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
Scratch register
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
XMIT FIFO
RESET CONTROL
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Read LSR/MR
Read RBR/MR
Read IR/write THR/MR
Master reset
Master reset
Master reset
Master reset
MR/FCR1 – FCR0/∆FCR0
MR/FCR2 – FCR0/∆FCR0
RESET STATE
All bits cleared (0 – 3 forced and 4 – 7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4 – 5 are
permanently cleared
All bits cleared
All bits cleared
All bits cleared (6 – 7 permanent)
Bits 5 and 6 are set; all other bits are cleared
Indeterminate
High
Low
Low
Low
No effect
No effect
No effect
No effect
All bits cleared
All bits cleared
November 2001 – Revised July 2003
SPRS007B
39
TI [ TEXAS INSTRUMENTS ]
