Functional Overview
S
e
l
e
c
t
Data
Bus
Buffer
8
Line
Control
Register
Receiver
Timing and
Control
8
Receiver
FIFO
Peripheral
Bus
Receiver
Buffer
Register
Receiver
Shift
Register
RX
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Line
Status
Register
Transmitter
FIFO
Transmitter
Holding
Register
Modem
Control
Register
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
8
Interrupt
Control
Logic
8
S
e
l
e
c
t
Transmitter
Timing and
Control
8
Transmitter
Shift
Register
TX
Control
Logic
8
INTRPT
(To CPU)
Figure 3–22. UART Functional Block Diagram
38
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
