SPRS439M – JUNE 2007 – REVISED AUGUST 2012
3
Functional Overview
M0 SARAM 1Kx16
(0-Wait)
M1 SARAM 1Kx16
(0-Wait)
L0 SARAM 4K x 16
(0-Wait, Dual Map)
L1 SARAM 4K x 16
(0-Wait, Dual Map)
L2 SARAM 4K x 16
(0-Wait, Dual Map)
Code
Security
Module
OTP 1K x 16
Flash
256K x 16
8 Sectors
Memory Bus
L3 SARAM 4K x 16
(0-Wait, Dual Map)
L4 SARAM 4K x 16
(0-W Data, 1-W Prog)
L5 SARAM 4K x 16
(0-W Data, 1-W Prog)
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
(0-W Data, 1-W Prog)
Memory Bus
TEST2
Pump
PSWD
Flash
Wrapper
TEST1
Boot ROM
8K x 16
XD31:0
FPU
XHOLDA
XHOLD
XREADY
32-bit CPU
(150 MHZ @ 1.9 V)
(100 MHz @ 1.8 V)
TCK
TDI
TMS
TDO
TRST
EMU0
EMU1
XZCS0
XZCS7
XZCS6
XINTF
88 GPIOs
GPIO
MUX
XR/W
DMA Bus
XWE0
XA0/XWE1
XA19:1
XCLKOUT
XRD
88 GPIOs
8 External Interrupts
Memory Bus
XCLKIN
CPU Timer 0
DMA
6 Ch
CPU Timer 1
CPU Timer 2
PIE
(Interrupts)
OSC,
PLL,
LPM,
WD
X1
X2
XRS
GPIO
MUX
A7:0
B7:0
REFIN
12-Bit
ADC
2-S/H
Memory Bus
XINTF
DMA Bus
16-bit peripheral bus
32-bit peripheral bus
(DMA accessible)
FIFO
(16 Levels)
McBSP-A/B
I2C
32-bit peripheral bus
FIFO
(16 Levels)
SCI-A/B/C
FIFO
(16 Levels)
SPI-A
ePWM-1/../6
eCAP-1/../6
HRPWM-1/../6
eQEP-1/2
CAN-A/B
(32-mbox)
SPISIMOx
SPISOMIx
EPWMxA
EPWMxB
SCIRXDx
SCITXDx
SPICLKx
ESYNCO
MCLKRx
SPISTEx
MCLKXx
CANRXx
EQEPxA
EQEPxB
EQEPxS
GPIO MUX
Secure zone
88 GPIOs
Figure 3-1. Functional Block Diagram
Copyright © 2007–2012, Texas Instruments Incorporated
Functional Overview
CANTXx
ESYNCI
EQEPxI
MFSRx
MFSXx
ECAPx
MDXx
MRXx
SDAx
SCLx
TZx
33
Product Folder Link(s):
TI [ TEXAS INSTRUMENTS ]
