TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174S–APRIL 2001–REVISED MARCH 2011
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VDDIO, VDD3VFL
VDDAn(A), VDDAIO
2.5 V
(3.3 V)
0.3 V
VDD, VDD1
[1.8 V (or 1.9 V)]
XCLKIN
X1
XCLKIN/8(B)
XCLKOUT
User-Code Dependent
tOSCST
tw(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/
Data/
Control
td(EX)
tsu(XPLLDIS)
XPLLDIS Sampling
User-Code Execution Phase
User-Code Dependent
th(XPLLDIS)
XF/XPLLDIS
XMP/MC
(Don’t Care)
GPIOF14
th(XMP/MC)
(Don’t Care)
(C)
th(boot-mode)
User-Code Dependent
Boot-Mode Pins
(D)
GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot Code
Boot-ROM Execution Starts
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. VDDAn – VDDA1/VDDA2 and AVDDREFBG
B. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at
XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.
C. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN
cycles from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is
based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or
without PLL enabled.
D. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches
at least 1 V and 3.3-V supply reaches 2.5 V.
Figure 6-11. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D)
104
Electrical Specifications
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