TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
9.1.15 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
must function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer
will wake the processor from IDLE mode.
STANDBY:
HALT:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
This mode basically shuts down the device and places it in the lowest possible power consumption mode. If the
internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep
these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU watchdog in this mode. If the on-chip crystal oscillator is used as
the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU
watchdog can wake the device from this mode.
The CPU clock (OSCCLK) and watchdog clock source should be from the same clock source before attempting
to put the device into HALT or STANDBY.
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
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