TMS320F240
DSP CONTROLLER
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
description (continued)
Table 1. Characteristics of the TMS320F240 DSP Controller
ON-CHIP MEMORY (WORDS)
RAM
DATA
288
DATA/PROG
256
FLASH
EEPROM
PROG
16K
5
50
PQ 132–P
POWER
SUPPLY
(V)
CYCLE
TIME
(ns)
PACKAGE
TYPE
PIN COUNT
architectural overview
The functional block diagram provides a high-level description of each component in the F240 DSP controller.
The TMS320F240 device is composed of three main functional units: a C2xx DSP core, internal memory, and
peripherals. In addition to these three functional units, there are several system-level features of the F240 that
are distributed. These system features include the memory map, device reset, interrupts, digital input/output
(I/O), clock generation, and low-power operation.
system-level functions
device memory map
The TMS320F240 implements three separate address spaces for program memory, data memory, and I/O.
Each space accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to
32K words at the top of the address range can be defined to be external global memory in increments of powers
of two, as specified by the contents of the global memory allocation register (GREG). Access to global memory
is arbitrated using the global memory bus request (BR) signal.
On the F240, the first 96 (0–5Fh) data memory locations are either allocated for memory-mapped registers or
are reserved. This memory-mapped register space contains various control and status registers including those
for the CPU.
All the on-chip peripherals of the F240 device are mapped into data memory space. Access to these registers
is made by the CPU instructions addressing their data-memory locations. Figure 1 shows the memory map.
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