TMS320F240
DSP CONTROLLER
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS
SPISIMO/IO
SPISOMI/IO
SPICLK/IO
SPISTE/IO
45
48
49
51
I/O
I/O
I/O
I/O
SPI slave in, master out , or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPI slave out, master in, or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPI clock, or general-purpose bidirectional I/O. This pin is configured as a digital input by all
device resets.
SPI slave transmit enable (optional), or general-purpose bidirectional I/O. This pin is configured
as a digital input by all device resets.
COMPARE SIGNALS
PWM1/CMP1
PWM2/CMP2
PWM3/CMP3
PWM4/CMP4
PWM5/CMP5
PWM6/CMP6
94
95
96
97
98
99
Compare or PWM outputs. The state of these pins is determined by the compare/PWM and
the full action control register (ACTR). CMP1–CMP6 go to the high-impedance state when un-
masked PDPINT goes active low.
After power up and PORESET is high, the PWM/CMP pins are high-impedance once the
internal clock is stable (see Figure 31 and Figure 32).
INTERRUPT AND MISCELLANEOUS SIGNALS
RS
35
I/O
Reset input. RS causes the TMS320F240 to terminate execution and sets PC = 0. When RS
is brought to a high level, execution begins at location zero of program memory. RS affects (or
sets to zero) various registers and status bits.
MP/MC (microprocessor/microcomputer) select. If MP/MC is low, internal program memory is
selected. If it is high, external program memory is selected.
Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state
of the INTM bit of the status register. NMI has programmable polarity.
Power-on reset. PORESET causes the TMS320F240 to terminate execution and sets PC = 0.
When PORESET is brought to a high level, execution begins at location zero of program
memory. PORESET affects (or sets to zero) the same registers and status bits as RS. In addi-
tion, PORESET initializes the PLL control registers.
External user interrupt no. 1
External user interrupt no. 2. General-purpose bidirectional I/O. This pin is configured as a
digital input by all device resets.
External user interrupt no. 3. General-purpose bidirectional I/O. This pin is configured as a
digital input by all device resets.
Maskable power-drive protection interrupt. If PDPINT is unmasked and it goes active low, the
timer compare outputs immediately go to the high-impedance state.
CLOCK SIGNALS
PLL oscillator output. XTAL2 is tied to one side of a reference crystal when the device is in PLL
mode (CLKMD[1:0] = 1x, CKCR0.7–6). This pin can be left unconnected in oscillator bypass
mode (OSCBYP
≤
VIL). This pin goes in the high-impedance state when EMU1/OFF is active
low.
PLL oscillator input. XTAL1/CLKIN is tied to one side of a reference crystal in PLL mode
(CLKMD[1:0] = 1x, CKCR0.7–6), or is connected to an external clock source in oscillator
bypass mode (OSCBYP
≤
VIL).
Bypass on-chip oscillator if low
O/Z
MP/MC
NMI
37
40
I
I
PORESET
41
I
XINT1
XINT2/IO
XINT3/IO
PDPINT
53
54
55
52
I
I/O
I/O
I
XTAL2
57
O
XTAL1/CLKIN
58
I/Z
OSCBYP
56
I
† I = input, O = output, Z = high impedance
8
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