ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢅ
ꢈ ꢂꢉ ꢊ ꢋꢌ ꢀ ꢍꢋꢎ ꢎ ꢏꢍ
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
description of group1 shared I/O pins (continued)
Table 2. Group1 Shared Pin Configurations
†
I/O PORT DATA AND DIRECTION
MUX CONTROL
REGISTER
(name.bit #)
PIN FUNCTION SELECTED
PIN #
(CRx.n = 1)
(CRx.n = 0)
REGISTER
DATA BIT #
DIR BIT #
72
73
OCRA.0
OCRA.1
OCRA.2
OCRA.3
OCRA.8
OCRA.9
OCRA.10
OCRA.11
OCRA.12
OCRA.13
OCRA.14
OCRA.15
OCRB.0
SYSCR.7–6
0 0
ADCIN0
ADCIN1
IOPA0
IOPA1
IOPA2
IOPA3
IOPB0
IOPB1
IOPB2
IOPB3
IOPB4
IOPB5
IOPB6
IOPB7
IOPC0
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PCDATDIR
0
1
2
3
0
1
2
3
4
5
6
7
0
8
9
90
ADCIN9
10
11
8
91
ADCIN8
100
101
102
105
106
107
108
109
63
PWM7/CMP7
PWM8/CMP8
PWM9/CMP9
T1PWM/T1CMP
T2PWM/T2CMP
T3PWM/T3CMP
TMRDIR
9
10
11
12
13
14
15
8
TMRCLK
ADCSOC
64
IOPC1
PCDATDIR
—
1
—
—
—
2
9
0 1
WDCLK
SYSCLK
CPUCLK
—
—
—
10
11
12
13
14
15
1 0
—
1 1
—
65
66
67
68
69
70
OCRB.2
OCRB.3
OCRB.4
OCRB.5
OCRB.6
OCRB.7
IOPC2
IOPC3
XF
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
BIO
3
CAP1/QEP1
CAP2/QEP2
CAP3
IOPC4
IOPC5
IOPC6
IOPC7
4
5
6
CAP4
7
†
Valid only if the I/O function is selected on the pin.
16
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