ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢅ
ꢈꢂꢉ ꢊꢋ ꢌ ꢀꢍ ꢋꢎ ꢎꢏ ꢍ
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
device memory map (continued)
Program
Program
Data
Hex
Hex
Hex
0000
0000
0000
Memory-Mapped
Registers and
Reserved
Interrupts
(On-Chip)
Interrupts
(External)
003F
003F
0040
005F
0060
0040
†
On-Chip ROM
(Flash EEPROM)
(8 x 2K Segments)
On-Chip
DARAM B2
3FFF
4000
007F
0080
External
Reserved
External
FDFF
FE00
FDFF
FE00
01FF
0200
On-Chip DARAM B0
(CNF = 1)
On-Chip DARAM B0
(CNF = 1)
On-Chip DARAM B0
(CNF = 0)
or
or
External (CNF = 0)
External (CNF = 0)
or
FEFF
FF00
FEFF
FF00
Reserved (CNF = 1)
Reserved
02FF
0300
Reserved
FFFF
On-Chip
DARAM B1
†
FFFF
ROM/Flash memory includes
address range 0000h–003Fh
03FF
0400
MP/MC = 1
Microprocessor
Mode
MP/MC = 0
Microcomputer
Mode
Reserved
Illegal
07FF
0800
6FFF
7000
Peripheral Memory-
Mapped Registers
(System, WD,
I/O
Hex
0000
ADC, SPI, SCI,
Interrupts, I/O)
73FF
7400
Peripheral
Memory-Mapped
Registers
External
(Event Manager)
743F
7440
Reserved
Illegal
FEFF
FF00
77FF
7800
Reserved
FF0E
7FFF
8000
Flash Control
Mode Register
External
FF0F
FF10
FFFF
Reserved
FFFE
FFFF
Wait-state Generator
Control Register
Figure 1. TMS320F240 Memory Map
13
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