TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
TMS320F206 Terminal Functions
TERMINAL
NAME
NO.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
41
40
39
38
36
34
33
32
31
29
28
27
26
24
23
22
74
73
72
71
69
68
67
66
64
62
61
60
58
57
56
55
TYPE†
DESCRIPTION
DATA AND ADDRESS BUSES
Parallel data bus D15 [most significant bit (MSB)] through D0 [least significant bit (LSB)]. D15–D0 are
used to transfer data between the TMS320F206 and external data / program memory or I / O devices.
Placed in the high-impedance state when not outputting (R / W high) or RS when asserted. They go into
the high-impedance state when OFF is active low.
I/O/Z
Parallel address bus A15 (MSB) through A0 (LSB). A15–A0 are used to address external data / program
memory or I / O devices. These signals go into the high-impedance state when OFF is active low.
O/Z
MEMORY CONTROL SIGNALS
PS
DS
IS
53
51
52
O/Z
O/Z
O/Z
Program-select signal. PS is always high unless low-level asserted for communicating to off-chip program
space. PS goes into the high-impedance state when OFF is active low.
Data-select signal. DS is always high unless low-level asserted for communicating to off-chip program
space. DS goes into the high-impedance state when OFF is active low.
I / O space-select signal. IS is always high unless low-level asserted for communicating to I/O ports. IS
goes into the high-impedance state when OFF is active low.
Data-ready input. READY indicates that an external device is prepared for the bus transaction to be
completed. If the external device is not ready (READY low), the TMS320F206 waits one cycle and checks
READY again. If READY is not used, it should be pulled high.
Read / write signal. R / W indicates transfer direction when communicating with an external device. R/W
is normally in read mode (high), unless low level is asserted for performing a write operation. R / W goes
into the high-impedance state when OFF is active low.
Read-select indicates an active, external read cycle. RD is active on all external program, data, and I / O
reads. RD goes into the high-impedance state when OFF is active low. The function of the RD pin can
be programmed to provide an inverted R/W signal instead of RD. The FRDN bit (bit 15) in the PMST
register controls this selection.
READY
49
I
R/W
47
O/Z
RD
45
O/Z
† I = input, O = output, Z = high impedance, PWR = power, GND = ground
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HOUSTON, TEXAS 77251–1443
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TI [ TEXAS INSTRUMENTS ]
