TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
Table 2. Legend for the ’F206 Internal Hardware Functional Block Diagram (Continued)
SYMBOL
PM
PREG
NAME
Product
Shift-Mode
Register Bits
Product Register
DESCRIPTION
These two bits identify which of the four product-shift modes (–6, 0, 1, 4) are used by PSCALE. PM resides
in ST1. See Table 6.
32-bit register holds results of 16
×
16 multiply.
0-, 1- or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the Data-Write Data Bus (DWEB), and requires no cycle
overhead.
16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
SSPCR is the control register for selecting the serial port’s mode of operation.
PSCALE
Product-Scaling
Shifter
TREG
Temporary
Register
Synchronous
Serial-Port Control
Register
Synchronous
Serial-Port
Transmit and
Receive Register
Timer-Control
Register
Timer-Period
Register
Timer-Counter
Register
Universal
Asynchronous
Receive/Transmit
Asynchronous
Serial-Port Control
Register
Asynchronous
Data Register
I / O Status
Register
Baud-Rate Divisor
Status Register
Interrupt Mask
Registers
Interrupt Flag
Register
Stack
SSPCR
SDTR
SDTR is the data-transmit and data-receive register.
TCR
TCR contains the control bits that define the divide-down ratio, start / stop the timer, and reload the period.
Also contained in TCR is the current count in the prescaler. Reset initializes the timer-divide-down ratio
to 0 and starts the timer.
PRD contains the 16-bit period that is loaded into the timer counter when the counter borrows or when the
reload bit is activated. Reset initializes the PRD to 0xFFFF.
TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF.
PRD
TIM
UART
UART is the asynchronous serial port.
ASPCR
ASPCR controls the asynchronous serial-port operation.
ADTR
IOSR
BRD
ST0
ST1
IMR
IFR
STACK
Asynchronous data-transmit and data-receive register
IOSR detects current levels (and changes with inputs) on pins IO0 – IO3 and the status of UART.
Used to set the baud rate of the UART
ST0 and ST1 contain the status of various conditions and modes. These registers can be stored in and
loaded from data memory, thereby allowing the status of the machine to be saved and restored.
IMR individually masks or enables the seven interrupts.
IFR indicates that the CPU has latched an interrupt pulse from one of the maskable interrupts.
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The ’C20x stack is 16-bit wide and eight-level deep.
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