TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
functional block diagram of the ’F206 internal hardware
DIV1
DIV2
IS
DS
PS
MUX
R/W
STRB
READY
BR
XF
HOLD
†
HOLDA
†
Program Bus
16
16
Program Bus
X1
CLKOUT1
CLKIN/X2
Control
Program Bus
16
RD
WE
NMI
PC
PAR
MSTACK
MUX
RS
Stack 8
×
16
MP/MC
INT[1–3]
3
FLASH EEPROM
(32K
×
16)
A15–A0
16
16
Program Control
(PCTRL)
16
16
16
16
MUX
D15–D0
16
16
16
Data Bus
Timer
TCR
TOUT
PRD
ARP(3)
TIM
3
ARB(3)
ASP
ADTR
TX
RX
I/O[0–3]
4
IOSR
BRD
MUX
3
16
3
3
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
ISCALE (0–16)
Multiplier
PREG(32)
32
PSCALE (–6, 0, 1, 4)
32
16
MUX
SSP
ARAU(16)
DX
CLKX
FSX
DR
FSR
CLKR
SSPCR
CALU(32)
16
SDTR
Memory Map
Register
IMR (16)
Reserved
IFR (16)
GREG (16)
I/O-Mapped Registers
32
Data/Prog
SARAM
(4K
×
16)
MUX
MUX
32
MUX
32
32
TREG0(16)
9
DP(9)
16
16
9
7
LSB
from
IR
16
16
16
16
MUX
Data Bus
MUX
Data/Prog
DARAM
B0 (256
×
16)
Data
DARAM
B2 (32
×
16)
B1 (256
×
16)
C ACCH(16)
ACCL(16)
32
MUX
MUX
16
OSCALE (0–7)
16
16
16
16
16
NOTES: A. Symbol descriptions appear in Table 3.
B. For clarity the data and program buses are shown as single buses although they include address and data bits.
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
Data Bus
NPAR
MUX
7
TI [ TEXAS INSTRUMENTS ]
