TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
PZ PACKAGE
( TOP VIEW )
V DD
A15
A14
A13
A12
V SS
A11
A10
A9
A8
V SS
A7
VDD
A6
A5
A4
V SS
A3
A2
A1
A0
V SS
PS
IS
DS
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
EMU0
EMU1 / OFF
TCK
TRST
TDI
TMS
TDO
V
SS
CLKR
FSR
DR
CLKX
V
SS
FSX
DX
V
DD
TOUT
TX
V
SS
RX
IO0
IO1
XF
BIO
RS
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
V
DD
READY
V
SS
R/W
STRB
RD
WE
BR
V
SS
D15
D14
D13
D12
V
SS
D11
V
DD
D10
D9
D8
D7
V
SS
D6
D5
D4
D3
Table 1 shows the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the execution
time of one machine cycle, and the type of package with total pin count of the TMS320F206 device.
Table 1. Characteristics of the TMS320F206 Processor
ON-CHIP MEMORY
DEVICE
DATA
TMS320F206
288
RAM
DATA/
PROG
4K + 256
ROM
PROG
–
FLASH
EEPROM
PROG
32K
I/O PORTS
POWER
SUPPLY
(V)
5
CYCLE
TIME
(ns)
50
PACKAGE
TYPE WITH
PIN COUNT
100-pin TQFP
2
POST OFFICE BOX 1443
TEST
MP / MC
DIV1
V CCP
DIV 2
HOLDA
V DD
IO2
IO3
PLL5V
V DD
CLKIN/X2
X1
VSS
CLKOUT1
V CCP
NMI
HOLD / INT1
INT2
INT3
VSS
D0
D1
D2
VSS
SERIAL
2
PARALLEL
64K
•
HOUSTON, TEXAS 77251–1443