TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.17 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between DM6437 and the
network. The DM6437 EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100
Mbps) in either half- or full-duplex mode. The EMAC module also supports hardware flow control and
quality of service (QOS) support.
The EMAC controls the flow of packet data from the DM6437 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame
will be detected as an error by the network.
Both the EMAC and the MDIO modules interface to the DM6437 device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
For the DM6437 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Module User's Guide (literature number SPRU941) which describes the DM6437 EMAC peripheral in
detail, see Section 2.9, Documentation Support section . For a list of supported registers and register
fields, see Table 6-81 [Ethernet MAC (EMAC) Control Registers] and Table 6-82 [EMAC Statistics
Registers] in this data manual.
6.17.1 EMAC Peripheral Register Description(s)
Table 6-81. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE
01C8 0000
01C8 0004
01C8 0008
01C8 0010
01C8 0014
01C8 0018
01C8 0080
01C8 0084
01C8 0088
01C8 008C
01C8 0090
01C8 00A0
01C8 00A4
01C8 00A8
01C8 00AC
01C8 00B0
01C8 00B4
01C8 00B8
01C8 00BC
01C8 0100
ACRONYM
TXIDVER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
TXCONTROL
TXTEARDOWN
Transmit Teardown Register
RXIDVER
Receive Identification and Version Register
Receive Control Register
RXCONTROL
RXTEARDOWN
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
RXMBPENABLE
Receive Teardown Register
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
274
Peripheral Information and Electrical Specifications
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