TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.15.1.1 McASP Block Diagram
Figure 6-42 illustrates the major blocks along with external signals of the TMS320DM6437 McASP0
peripheral; and shows the 4 serial data [AXR] pins.
McASP0
Transmit
DIT
RAM
Frame Sync
Generator
AFSX0
T
ransmit
Clock Check
(High-
Transmit
Clock
Generator
AHCLKX0
ACLKX0
Frequency)
AMUTE0
Error
Detect
AMUTEIN0
Receive
Clock Check
(High-
Receive
Clock
Generator
AHCLKR0
ACLKR0
Frequency)
Transmit
Data
Formatter
Receive
Frame Sync
Generator
AFSR0
Serializer 0
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
Serializer 1
Serializer 2
Serializer 3
Receive
Data
Formatter
GPIO
Control
Figure 6-42. McASP0 Configuration
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