TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-69. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1(1)(2)
(see Figure 6-41)
-400
-500
-600
NO.
UNIT
MASTER
SLAVE
MIN
MIN
14
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 - 3P
5+ 6P
ns
ns
(1) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
(2) For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
Table 6-70. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1(1)(2) (see Figure 6-41)
-400
-500
-600
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
MAX
1
2
3
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXH-DXV)
Hold time, FSX low after CLKX high(4)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX high to DX valid
H - 4
T - 2
-4
H + 5.5
T + 1
5.5
ns
ns
ns
3P + 2.8
3P + 2
2P + 2
5P + 17
5P + 17
4P + 17
Disable time, DX high impedance following
last data bit from CLKX high
6
7
tdis(CKXH-DXHZ)
td(FXL-DXV)
-6
7.5
ns
ns
Delay time, FSX low to DX valid
L - 2
L+ 4
(1) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
(2) For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK3 period)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 6-41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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